ISR Latency - Complete Guide to Ultra-Fast Interrupt Response in Embedded Systems

What Is ISR Latency?

ISR latency is the time between a hardware interrupt request and the moment your Interrupt Service Routine actually begins execution.

Interrupt latency typically includes:

• Hardware latency – delay from the peripheral raising an interrupt to the CPU detecting it.
• CPU entry latency – finishing the current instruction, pushing context, jumping to the vector table.
• Handler latency – time before your ISR code starts executing.
• Response time – how long it takes for the ISR to trigger the required action.

Firmware engineers mostly optimize the last two stages, which have the greatest effect on interrupt handling in embedded systems.

Interrupt Latency – A Quick Overview

How the Interrupt Response Pipeline Works

When an interrupt occurs, the CPU follows this sequence:

• Recognize the interrupt request
• Complete the current instruction
• Save registers and context
• Jump to the ISR vector
• Execute your ISR code

Each stage contributes to interrupt latency, especially on high-performance cores with deeper pipelines.
On compact microcontrollers like Cortex-M, latency is lower due to simpler pipelines and hardware features like tail-chaining.

Example – Measuring ISR Entry Delay

A common way to measure interrupt latency is to toggle a GPIO at the first instruction inside the ISR:

void EXTI0_IRQHandler(void)
{
    GPIO_TogglePin(TEST_PIN); // first instruction
    // ISR logic here
}

Use an oscilloscope or logic analyzer to measure the delay between:

• The hardware event signal
• The rising edge on your test pin

This directly shows interrupt response time and helps evaluate jitter.

Microarchitectural Factors That Affect ISR Latency

Several hardware-level behaviors influence how quickly an ISR begins execution:

• Pipeline depth
  • Shallow pipelines (Cortex-M) enter ISRs faster
  • Deep pipelines (Cortex-A) require more cycles to flush and switch modes
• Interrupt masking
  • Interrupts may be briefly disabled during critical code sections
  • Atomic operations
  • Flash erase or programming
  • RTOS kernel updates
• Bus contention
  • AHB/APB buses congested
  • Flash wait states
  • DMA and CPU memory competition
• Cache behavior
  • I-cache miss during ISR entry
  • D-cache eviction during stack push
  • TLB miss

How to Reduce Interrupt Latency

1. Prioritize Critical ISRs
   • Assign highest priority to time-sensitive interrupts
   • Avoid priority inversion
   • Keep critical ISRs above RTOS syscall thresholds
2. Use a Top-Half / Bottom-Half Design
   • Top-half: ultra-fast, essential work
   • Bottom-half: processing in tasks/handlers
3. Avoid Function Calls in ISRs
   • Use static inline, macros, direct register access
4. Place ISR Code in TCM or SRAM
   • Flash adds wait states
   • TCM = single-cycle access
5. Avoid Heavy Operations
   • No printf/logging
   • No dynamic memory
   • No floating point operations
   • No large data copies
6. Zero-Copy Data Handling
   • Ring buffers
   • Pre-allocated memory
7. Use DMA for Deterministic Transfers
   • ISR only handles start/end events

ISR Design Techniques for Better Performance

• Tail-chaining (Cortex-M)
  • Hardware reuses stacked context
  • Reduces entry and exit time
• Reduce Stack Usage
  • Small stacks → fewer memory cycles
• Avoid Shared Resources
  • Flash controller
  • DMA
  • High-bandwidth peripherals

Common Mistakes to Avoid

• Long ISR logic
• Using printf or malloc inside ISRs
• Frequently disabling interrupts
• Not measuring worst-case latency
• Ignoring jitter in time-critical loops
• Running heavy tasks at high interrupt priority

Summary – ISR Latency Optimization

Optimizing ISR latency means designing a predictable, minimal, and carefully structured interrupt pipeline. With proper memory placement, DMA usage, priority mapping, and zero-copy methods, embedded systems can achieve extremely fast and stable interrupt response time.