8051 interrupts are a core feature that enable real-time event handling in embedded systems. Instead of continuously polling peripherals, the microcontroller responds immediately when a specific event occurs. This improves system efficiency, response time, and reliability. In this article, you will learn the complete 8051 interrupt architecture, types of interrupts, interrupt priority, vector table, and working mechanism with assembly programs and real-time applications.
The 8051 microcontroller supports five interrupt sources.
| Interrupt | Source | Trigger Condition | Vector Address | Flag |
|---|---|---|---|---|
| INT0 | P3.2 | Falling edge / Low level | 0003H | IE0 |
| Timer0 | TF0 | Timer overflow | 000BH | TF0 |
| INT1 | P3.3 | Falling edge / Low level | 0013H | IE1 |
| Timer1 | TF1 | Timer overflow | 001BH | TF1 |
| Serial | RI / TI | Data receive / transmit | 0023H | RI / TI |
When an event occurs, the corresponding flag bit is set automatically.
| Event | Flag Bit |
|---|---|
| External INT0 | IE0 |
| Timer0 overflow | TF0 |
| External INT1 | IE1 |
| Timer1 overflow | TF1 |
| Serial Rx / Tx | RI / TI |
The CPU checks the EA bit (IE.7):
EA = 1 → Interrupts enabled
EA = 0 → All interrupts disabled
| Interrupt | Enable Bit |
|---|---|
| INT0 | EX0 |
| Timer0 | ET0 |
| INT1 | EX1 |
| Timer1 | ET1 |
| Serial | ES |
If multiple interrupts occur simultaneously:
IP bit = 1 → High priority
IP bit = 0 → Low priority
High-priority interrupts can interrupt low-priority ISRs.
The current Program Counter (PC) value is pushed onto the stack.
| Interrupt | Vector Address |
|---|---|
| INT0 | 0003H |
| Timer0 | 000BH |
| INT1 | 0013H |
| Timer1 | 001BH |
| Serial | 0023H |
The Interrupt Service Routine executes the required task.
The RETI instruction:
Pops the saved PC from the stack
Returns control to the main program
| Step | Operation |
|---|---|
| 1 | Event occurs and flag is set |
| 2 | CPU checks IE register |
| 3 | Priority is verified |
| 4 | Program Counter saved |
| 5 | CPU jumps to ISR |
| 6 | ISR executes |
| 7 | RETI returns control |
ORG 0000H LJMP MAIN ORG 000BH LJMP TIMER_ISR MAIN: MOV TMOD, #01H MOV TH0, #0FCH MOV TL0, #18H SETB TR0 SETB ET0 SETB EA SJMP $ TIMER_ISR: CLR TF0 MOV TH0, #0FCH MOV TL0, #18H RETI END
ORG 0000H LJMP MAIN ORG 000BH LJMP TIMER0_ISR MAIN: MOV TMOD, #01H MOV TH0, #0FCH MOV TL0, #018H SETB P1.0 SETB ET0 SETB EA SETB TR0 HERE: SJMP HERE TIMER0_ISR: CLR TR0 CLR TF0 MOV TH0, #0FCH MOV TL0, #018H CPL P1.0 SETB TR0 RETI END
ORG 0000H LJMP MAIN ORG 001BH LJMP TIMER1_ISR MAIN: MOV TMOD, #50H MOV TH1, #00H MOV TL1, #00H SETB ET1 SETB EA SETB TR1 HERE: SJMP HERE TIMER1_ISR: CLR TR1 MOV P1, TL1 MOV TH1, #00H MOV TL1, #00H SETB TR1 RETI END
Interrupts are the backbone of real-time embedded systems. By using the interrupt structure, IE register, IP register, vector table, and ISR routines, the 8051 microcontroller can respond instantly to external and internal events without wasting CPU resources. Mastering 8051 interrupts is essential for building reliable, efficient, and industry-ready embedded applications.
Interrupts allow immediate response to events without continuous polling, making systems faster and efficient.
The IE register enables or disables individual interrupts and controls the global interrupt enable.
The IP register assigns priority levels to interrupts when multiple interrupts occur.
The interrupt with higher priority, as defined by the IP register, is serviced first.
Author
Embedded Systems Trainer – IIES
Updated On: 29-12-25