LPC1768 Programming: Interrupts, NVIC, Timer & GPIO Guide

What Is an Interrupt in LPC1768 Programming?

An interrupt is a mechanism that temporarily changes the normal execution flow of a program when a specific event occurs.

Consider an embedded application in which an LED needs to turn ON when a push button is pressed. A simple approach is to continuously check the button status inside the main loop:

while(1)
{
    if(switch_pressed)
    {
        LED_ON();
    }
}

This approach is called polling. The processor repeatedly checks whether the event has occurred, even when nothing has changed.

With an interrupt, the processor can continue executing its normal application. When the button generates an interrupt, the processor detects the event and transfers execution to an Interrupt Service Routine (ISR).

The basic execution flow is:

This event-driven approach is particularly useful in real-time embedded systems because the processor does not need to continuously monitor every peripheral.

Why Are Interrupts Important in Embedded Systems?

Microcontrollers frequently interact with hardware events that can occur at unpredictable times. A button may be pressed, a UART byte may arrive, a timer may reach its match value, or an external sensor may generate a signal.

Without interrupts, software may need to repeatedly check each peripheral. As the number of peripherals increases, this polling approach can consume processor time and make the application more difficult to organize.

Interrupts allow the LPC1768 to respond when an event actually occurs. This makes them useful for applications involving push buttons, periodic sensor sampling, UART communication, ADC conversion, CAN communication, motor control, industrial automation, and real-time monitoring.

For this reason, understanding LPC1768 interrupt programming is an important part of learning LPC1768 programming and Embedded C development.

LPC1768 Interrupt Architecture

The LPC1768 uses the ARM Cortex-M3 Nested Vectored Interrupt Controller (NVIC) to manage interrupts generated by different peripherals.

A simplified interrupt path is:

The peripheral generates an interrupt request when its configured event occurs. The NVIC receives and manages that interrupt request and transfers processor execution to the appropriate interrupt handler.

The NVIC also provides interrupt enabling, disabling, priority configuration, and nested interrupt handling.

This architecture is one of the key concepts behind LPC1768 NVIC programming.

What Is NVIC?

NVIC stands for Nested Vectored Interrupt Controller. It is an interrupt controller integrated into the ARM Cortex-M3 processor.

In LPC1768 programming, the NVIC is used to control the interrupt sources generated by peripherals.

For example, Timer0 can be enabled using:

NVIC_EnableIRQ(TIMER0_IRQn);

This enables the Timer0 interrupt at the NVIC level.

Similarly:

NVIC_DisableIRQ(TIMER0_IRQn);

disables the Timer0 interrupt.

Configuring the peripheral alone is therefore not always sufficient. The corresponding interrupt must also be enabled in the NVIC before the processor can respond to it.

What Is an Interrupt Service Routine?

An Interrupt Service Routine (ISR) is the function executed when a particular interrupt occurs.

For Timer0, the handler can be written as:

void TIMER0_IRQHandler(void)
{
    // Interrupt handling code
}

The ISR name depends on the interrupt source. For example, TIMER0_IRQHandler() handles Timer0 interrupts, while TIMER1_IRQHandler() handles Timer1 interrupts.

An external interrupt can use a handler such as EINT0_IRQHandler().

LPC1768 Timer Interrupt

A timer interrupt occurs when a timer reaches a configured match value or another configured timer event takes place.

For example, Timer0 can be configured to generate an interrupt periodically. The basic flow is:

The advantage of using a timer interrupt is that the processor does not need to continuously wait for the timer event or depend on software delay loops.

This makes the LPC1768 timer interrupt useful for periodic tasks such as sensor sampling, timing operations, LED control, digital clocks, and other real-time functions.

LPC1768 Timer0 Interrupt Example

A basic Timer0 interrupt configuration can be structured as follows:

#include 

void Timer0_Init(void)
{
    LPC_SC->PCONP |= (1 << 1); LPC_TIM0->PR = 23;

    LPC_TIM0->MR0 = 1000000;

    LPC_TIM0->MCR = (1 << 0) | (1 << 1); LPC_TIM0->TCR = 1;

    NVIC_EnableIRQ(TIMER0_IRQn);
}

void TIMER0_IRQHandler(void)
{
    LPC_TIM0->IR = (1 << 0);

    // Interrupt task
}

int main(void)
{
    Timer0_Init();

    while(1)
    {
        // Main application
    }
}

The important concept in this LPC1768 programming example is that the CPU does not continuously wait for the timer event.

When the Timer0 match occurs, the timer generates an interrupt request. The NVIC then transfers execution to TIMER0_IRQHandler().

After the interrupt handler completes, execution returns to the main application.

Understanding LPC1768 Timer Interrupt Registers

Several timer registers participate in the interrupt configuration.

Prescale Register — PR

The Prescale Register (PR) controls the relationship between the peripheral clock and the Timer Counter.

For example:

LPC_TIM0->PR = 23;

If the timer peripheral clock is 24 MHz:

Therefore, each Timer Counter increment represents approximately 1 microsecond.

Match Register — MR0

The Match Register 0 (MR0) stores the value against which the Timer Counter is compared.

For example:

LPC_TIM0->MR0 = 1000000;

With a 1 MHz timer counter, the match occurs after approximately:

The match event can then generate the configured Timer0 interrupt.

Match Control Register — MCR

The Match Control Register (MCR) determines what happens when a timer match occurs.

For example:

LPC_TIM0->MCR = (1 << 0) | (1 << 1);

This configuration enables an interrupt on the MR0 match and resets the timer after the match.

Interrupt Register — IR

The Interrupt Register (IR) indicates which timer interrupt condition has occurred.

Inside the ISR, the interrupt condition should be cleared correctly.

For MR0:

LPC_TIM0->IR = (1 << 0);

Clearing the interrupt condition is important because the interrupt source must be acknowledged correctly.

GPIO and External Interrupts in LPC1768

The LPC1768 can also respond to external signals through its external interrupt inputs, including EINT0, EINT1, EINT2, and EINT3.

These inputs can be connected to devices such as push buttons, sensors, motion detectors, external controllers, and event detection circuits.

A typical external interrupt sequence is:

For example, an external interrupt 0 handler can be written as:

void EINT0_IRQHandler(void)
{
    // Handle external interrupt

    LPC_SC->EXTINT = (1 << 0);
}

The interrupt flag is cleared after handling the event.

This type of LPC1768 external interrupt programming is useful when the microcontroller needs to respond to an external hardware event rather than repeatedly checking the input state.

Edge-Triggered and Level-Triggered Interrupts

External interrupts can be configured according to how the input signal should activate the interrupt.

In edge-triggered operation, the interrupt occurs when the signal changes state.

A rising edge represents LOW → HIGH. A falling edge represents HIGH → LOW.

Edge-triggered interrupts are useful when detecting events such as button transitions or sensor pulses.

In level-triggered operation, the interrupt is generated while the signal remains at a particular configured logic level.

For example, the system may respond to a LOW level or HIGH level depending on the application requirements.

The appropriate interrupt configuration depends on the hardware and the way the external signal needs to be processed.

Interrupt Priority in LPC1768 NVIC

Interrupt priority is another important part of LPC1768 NVIC programming.

When multiple interrupt sources are available, the configured priority determines how the processor handles competing interrupt events.

For example:

NVIC_SetPriority(TIMER0_IRQn, 3);

This assigns a priority level to the Timer0 interrupt.

Priority becomes particularly important in real-time embedded applications where multiple peripherals need to respond quickly.

The Cortex-M3 NVIC also supports nested interrupt handling according to the configured priority system. This allows interrupt-driven applications to manage multiple event sources more effectively.

Common LPC1768 Interrupt Programming Mistakes

Forgetting to Enable the NVIC

Configuring the peripheral interrupt is not always enough. The corresponding interrupt must also be enabled in the NVIC.

NVIC_EnableIRQ(TIMER0_IRQn);

If the NVIC interrupt is not enabled, the expected ISR may not execute even though the timer peripheral has been configured.

Using the Wrong ISR Name

The interrupt handler name must correspond to the vector table definition.

For Timer0:

void TIMER0_IRQHandler(void)

Using an incorrect handler name can prevent the expected interrupt routine from being called.

Not Clearing the Interrupt Flag

The interrupt condition should be cleared after handling the event.

For Timer0 MR0:

LPC_TIM0->IR = (1 << 0);

Failing to clear the interrupt condition correctly can cause repeated interrupt requests or unexpected program behavior.

Making the ISR Too Large

An ISR should generally perform only the work necessary to respond to the interrupt.

Large delays, lengthy calculations, and complex processing inside an ISR can reduce the responsiveness of the rest of the application. Time-consuming operations are generally better handled outside the interrupt routine when the application architecture permits it.

Practical Applications of LPC1768 Interrupts

Interrupt-driven programming is useful across many embedded applications. A Timer0 interrupt can periodically trigger a sensor-reading task, while a UART interrupt can respond when communication data arrives.

The same approach can be applied to button detection, digital clocks, motor control, ADC data processing, CAN communication, industrial automation, automotive electronics, and real-time monitoring systems.

For example, a sensor-based application may use a timer interrupt to establish a periodic sampling interval. An external interrupt can then respond immediately to a hardware event, while the main program continues performing other application-level tasks.

This event-driven architecture is one of the reasons interrupts are fundamental to real-time embedded programming.

Conclusion

Once these concepts are understood, developers can build a stronger foundation in LPC1768 Embedded C programming and apply interrupt-driven techniques to real-time embedded applications.