If you’ve worked with ARM processors, Embedded Linux, Raspberry Pi, Android devices, or modern SoCs, you’ve likely come across the term AArch64. It is the 64-bit execution state introduced with the ARMv8-A architecture, designed to improve performance, expand memory addressing, and support modern computing workloads.
Today, AArch64 powers billions of devices, from smartphones and tablets to cloud servers, automotive systems, networking equipment, and high-performance embedded platforms. Understanding AArch64 is essential for embedded engineers, firmware developers, Linux programmers, and anyone working with ARM-based processors.
AArch64 is one of the execution states defined in the ARMv8-A architecture.
Instead of simply extending the older 32-bit instruction set, ARM designed a new 64-bit architecture with improved efficiency and cleaner instruction encoding.
AArch64 has become the standard execution mode for modern ARM processors because it offers several advantages over older 32-bit architectures.
It enables:
Many ARMv8-A and ARMv9-A processors support AArch64, including:
These processors power smartphones, Raspberry Pi boards, cloud servers, automotive systems, and embedded Linux devices.
ARM architecture has evolved significantly over the years.
ARM Version | Execution State | Word Size | Major Improvement |
ARMv6 | AArch32 | 32-bit | Mobile processors |
ARMv7-A | AArch32 | 32-bit | Cortex-A series |
ARMv8-A | AArch32 + AArch64 | 32 & 64-bit | Introduction of AArch64 |
ARMv9-A | AArch64 | 64-bit | Security and AI enhancements |
Modern ARM processors can often run both 32-bit and 64-bit software for compatibility.
Many ARM processors support both execution states.
Execution State | Purpose |
AArch32 | Runs older 32-bit applications |
AArch64 | Runs modern 64-bit applications |
This dual support provides backward compatibility while allowing developers to benefit from modern 64-bit capabilities.
Many people use these terms interchangeably, but they have slightly different meanings.
ARM64 | AArch64 |
Marketing/common name | Official ARM architecture term |
Commonly used by Linux and Android | Defined by ARM architecture documentation |
Refers to 64-bit ARM systems | Refers to the 64-bit execution state |
Used in package names and operating systems | Used in technical documentation |
ARM introduced the name AArch64 to clearly distinguish the execution state from the processor architecture.
ARMv8-A defines two execution states:
Using the names AArch32 and AArch64 keeps the terminology consistent across different ARM processor families and architecture versions.
Operating systems and software distributions often use ARM64 because it is simpler and easier to recognize, while ARM’s official documentation uses AArch64.
A typical AArch64 processor consists of several major components.
Together, these components execute instructions efficiently while supporting multitasking, memory protection, and modern operating systems.
One of the biggest improvements in AArch64 is the expanded register set.
Register | Description |
X0–X30 | 64-bit general-purpose registers |
W0–W30 | Lower 32 bits of X registers |
X31 | Stack Pointer (SP) or Zero Register (XZR), depending on instruction |
PC | Program Counter |
Register | Size |
V0–V31 | 128-bit |
These registers are used for:
Unlike older ARM architectures, AArch64 uses a cleaner instruction set.
AArch64 follows a load/store architecture, meaning arithmetic and logical operations work only on registers.
Memory access flow:
Memory
│
▼
Load Instruction
│
▼
Registers
│
Arithmetic / Logic
│
▼
Registers
│
Store Instruction
│
▼
Memory
Data Type | Size |
Byte | 8 bits |
Halfword | 16 bits |
Word | 32 bits |
Doubleword | 64 bits |
Quadword | 128 bits |
AArch64 introduces several architectural improvements over older ARM execution states.
When a program runs in AArch64 mode, the processor follows a sequence of operations.
Application
│
▼
Instruction Fetch
│
▼
Instruction Decode
│
▼
Read Registers
│
▼
Execute Instruction
│
▼
Memory Access (if required)
│
▼
Write Result Back
│
▼
Next Instruction
If required:
Instead of traditional processor modes, AArch64 uses Exception Levels (ELs). There are four exception levels.
Exception Level | Purpose |
EL0 | User applications |
EL1 | Operating system kernel |
EL2 | Hypervisor (Virtual Machines) |
EL3 | Secure Monitor / Trusted Firmware |
Runs normal applications such as:
Characteristics:
Runs the operating system kernel. Responsibilities include:
Used for virtualization. Responsibilities:
Common usage:
Highest privilege level. Used for:
EL3
▲
│
EL2
▲
│
EL1
▲
│
EL0
Higher levels can control lower levels.
The MMU converts virtual addresses into physical addresses.
Without an MMU:
CPU
│
▼
Physical Memory
With an MMU:
CPU
│
▼
Virtual Address
│
▼
MMU
│
▼
Physical Address
Virtual memory allows every process to have its own address space.
Advantages:
Modern AArch64 processors use multiple cache levels.
Cache | Purpose |
L1 Cache | Fastest access |
L2 Cache | Shared cache |
L3 Cache | Large shared cache (high-end processors) |
Benefits:
Most AArch64 processors use pipelining to execute multiple instructions simultaneously.
Typical stages include:
Benefits:
Branch prediction helps reduce delays caused by conditional instructions. Instead of waiting for a branch decision, the processor predicts the next instruction.
Benefits:
NEON is ARM’s SIMD (Single Instruction Multiple Data) engine. It allows one instruction to process multiple data elements simultaneously.
Common applications:
The FPU performs floating-point calculations efficiently.
Typical workloads:
AArch64 includes several built-in security mechanisms.
Helps prevent unauthorized memory access.
Randomizes memory locations to make attacks more difficult.
Available in newer ARM architectures.
Benefits:
Protects against branch injection attacks.
Separates execution into:
Common uses:
AArch64 provides hardware support for virtualization.
Advantages:
Used in:
ARM processors are known for excellent performance per watt.
Reasons include:
This makes AArch64 suitable for:
.global _start
_start:
MOV X0, #10
MOV X1, #20
ADD X2, X0, X1
RET
Instruction | Description |
MOV X0, #10 | Load 10 into X0 |
MOV X1, #20 | Load 20 into X1 |
ADD X2, X0, X1 | Add X0 and X1, store result in X2 |
RET | Return from function |
Result: X2 = 30
Feature | AArch64 | x86-64 |
Architecture | RISC | CISC |
Instruction Length | Fixed (32-bit) | Variable |
Power Consumption | Lower | Higher |
Performance per Watt | Excellent | Good |
Mobile Devices | Dominant | Rare |
Desktop PCs | Growing | Dominant |
Servers | Rapidly Growing | Widely Used |
Instruction Complexity | Simpler | More Complex |
Decoding | Easier | More Complex |
Feature | AArch32 | AArch64 |
Register Size | 32-bit | 64-bit |
Address Space | Smaller | Much Larger |
Registers | 16 | 31 General-Purpose Registers |
Instruction Set | Older | Redesigned |
Performance | Lower | Higher |
Memory Support | Limited | Large Memory Support |
Compiler Optimization | Good | Better |
AArch64 powers a wide range of modern computing platforms.
Follow these practices while learning or developing software for AArch64 systems.
Understand:
A strong foundation makes debugging and optimization much easier.
Common optimization levels:
Always test your application after changing optimization levels.
Using the correct calling convention helps ensure compatibility between libraries, operating systems, and compilers.
Memory access is slower than register access.
Good practice:
Refer to official resources from:
Official manuals provide the most accurate architectural details.
Small optimizations can significantly improve AArch64 application performance.
Access registers instead of memory whenever possible.
NEON can greatly improve performance in:
Common options: -O2 or -O3. Choose the optimization level based on performance and code size requirements.
Use profiling tools to identify actual bottlenecks instead of optimizing code blindly.
AArch64 is typically covered as part of advanced embedded systems and Embedded Linux training.
At the Indian Institute of Embedded Systems (IIES), Bangalore, students gain practical exposure to ARM-based development through embedded systems, Embedded Linux, and ARM processor programming. Learning topics such as ARM architecture, C programming, Embedded C, Linux fundamentals, and debugging provides a strong foundation for understanding AArch64-based platforms used in modern embedded applications.
AArch64 continues to evolve with newer ARM architectures. Some key trends include:
Understanding what is AArch64 is essential for anyone working with modern ARM-based systems. As the 64-bit execution state of the ARM architecture, AArch64 introduces a redesigned instruction set, expanded register file, larger memory addressing, improved security, and higher performance compared to AArch32.
From smartphones and Embedded Linux boards to automotive electronics and cloud servers, AArch64 powers many of today’s computing platforms. Building a solid understanding of its architecture, register set, exception levels, and memory model prepares students and developers for embedded software, firmware, Linux, and system programming roles.
In most practical situations, yes. ARM64 is the commonly used name in operating systems and software, while AArch64 is ARM’s official architectural term for the 64-bit execution state.
ARM introduced AArch64 to overcome the limitations of 32-bit processors. It provides larger memory addressing, more registers, better performance, improved security, and support for modern computing workloads.
Yes. Many ARMv8-A processors support both AArch32 and AArch64, allowing compatible operating systems to run both 32-bit and 64-bit applications.
AArch64 is widely used in smartphones, Embedded Linux boards, Raspberry Pi, automotive systems, networking devices, industrial controllers, AI edge devices, and ARM-based cloud servers.
AArch64 provides 31 general-purpose 64-bit registers (X0–X30) along with dedicated registers such as the Stack Pointer (SP), Program Counter (PC), and floating-point/SIMD registers (V0–V31).
Author
Embedded Systems trainer – IIES
Updated On: 10-07-26