What Is an Interrupt Controller?
An Interrupt Controller is a specialized hardware unit that sits between interrupt-generating peripherals and the processor. Its primary role is to receive multiple interrupt requests, determine which request should be serviced based on priority, and notify the CPU accordingly.
Instead of connecting every peripheral directly to the processor, devices send their interrupt signals to the interrupt controller. The controller organizes these requests, applies priority rules, supports interrupt masking, and ensures that the processor receives interrupts in a controlled manner.
Modern interrupt controllers also support advanced capabilities such as interrupt nesting, software-generated interrupts, vector-based interrupt handling, and configurable priority levels.
Architecture
Timer
│
UART
│
ADC
│
GPIO
│
SPI
│
I2C
│
▼
+----------------------+
| Interrupt Controller |
+----------------------+
│
▼
CPU
│
▼
Interrupt Service
Routine (ISR)
How Do Interrupts Work?
Interrupts eliminate the need for continuous polling. Instead of repeatedly checking whether a peripheral requires attention, the processor continues executing its main program until an interrupt request is generated.
Interrupt Processing Flow
Peripheral Event
│
▼
Interrupt Generated
│
▼
Interrupt Controller
│
▼
Interrupt Enabled?
│
Yes │ No
▼
Priority Evaluation
│
▼
Highest Priority Selected
│
▼
CPU Interrupt
│
▼
ISR Executes
│
▼
Interrupt Cleared
│
▼
Resume Main Program
Example: UART Data Reception
Consider a UART receiving data from a computer.
Without interrupts:
- CPU repeatedly checks UART registers.
- Most checks find no new data.
- CPU time is wasted.
With interrupts:
- CPU performs other tasks.
- UART generates an interrupt only when data arrives.
- Interrupt controller forwards the request.
- CPU processes the received data immediately.
This event-driven approach improves performance and reduces unnecessary processor activity.
Main Functions of an Interrupt Controller
An interrupt controller performs much more than simply forwarding interrupt requests. It acts as the decision-making unit for interrupt management.
1. Collects Interrupt Requests
Receives interrupt signals from multiple hardware peripherals simultaneously.
Examples include:
- GPIO
- UART
- SPI
- I2C
- Timers
- ADC
- DMA
- Ethernet controllers
2. Prioritizes Interrupts
Not every interrupt has the same level of importance.
| Interrupt Source | Typical Priority |
| Emergency Shutdown | Very High |
| Motor Control Timer | High |
| CAN Communication | High |
| UART Reception | Medium |
| ADC Conversion | Medium |
| Push Button | Low |
Critical events are serviced before less important requests.
3. Masks or Disables Interrupts
The controller allows specific interrupts to be temporarily disabled while others remain active.
This is useful when:
- Updating shared variables
- Performing critical firmware operations
- Preventing unwanted nested interrupts
- Initializing hardware safely
4. Supports Interrupt Nesting
If a higher-priority interrupt occurs while another ISR is executing, the controller can temporarily suspend the current ISR and service the more critical interrupt first.
This behavior is essential in:
- Automotive systems
- Medical devices
- Industrial automation
- Flight control systems
5. Identifies the Interrupt Source
The controller informs the processor which peripheral generated the interrupt. This allows the CPU to execute the correct Interrupt Service Routine without checking every device individually.
6. Routes Interrupts to the Processor
After evaluating pending requests and priority levels, the interrupt controller forwards the appropriate interrupt signal to the CPU for servicing.
Key Takeaways
- Collects interrupt requests from multiple peripherals.
- Assigns priorities to interrupt sources.
- Supports interrupt masking and enabling.
- Identifies the correct interrupt source.
- Enables interrupt nesting for real-time responsiveness.
- Reduces processor workload through centralized interrupt management.
Interrupt Controller Major Components
| Component | Purpose |
| Interrupt Inputs | Receive interrupt requests from peripherals |
| Pending Register | Stores active interrupt requests |
| Enable Register | Enables or disables interrupts |
| Priority Registers | Define servicing priority |
| Mask Register | Temporarily blocks selected interrupts |
| Vector Logic | Identifies the correct ISR |
| CPU Interface | Sends interrupt signals to the processor |
Working Principle of an Interrupt Controller
The interrupt controller continuously monitors interrupt signals from connected peripherals. When one or more interrupts occur, it evaluates their priority and determines whether the interrupt is enabled.
If multiple interrupts are pending, the controller selects the highest-priority request and forwards it to the processor. The CPU saves its current execution context, jumps to the corresponding ISR, completes the required task, clears the interrupt, and resumes normal program execution.
Interrupt controller processing multiple interrupt requests.
Step-by-Step Working
- Peripheral detects an event.
- Interrupt request is generated.
- Interrupt controller receives the request.
- Pending interrupt is recorded.
- Priority is evaluated.
- Highest-priority enabled interrupt is selected.
- CPU acknowledges the interrupt.
- ISR executes.
- Interrupt flag is cleared.
- CPU resumes the interrupted task.
Features of an Interrupt Controller
Modern interrupt controllers include several features that improve interrupt handling and overall system performance.
1. Interrupt Prioritization
- Assigns priority to each interrupt.
- Services higher-priority interrupts before lower-priority ones.
- Essential for real-time and safety-critical applications.
2. Interrupt Masking
- Temporarily disables selected interrupts.
- Prevents interruptions during critical operations.
- Allows other interrupts to remain active.
3. Interrupt Nesting
- Allows a higher-priority interrupt to interrupt a lower-priority ISR.
- Improves response time for critical events.
4. Interrupt Vectoring
- Directly identifies the correct Interrupt Service Routine (ISR).
- Reduces software overhead.
- Enables faster interrupt handling.
5. Interrupt Pending Status
- Records interrupts waiting to be serviced.
- Prevents interrupt requests from being missed.
6. Interrupt Enable and Disable Control
- Enables or disables individual interrupt sources.
- Provides flexible interrupt configuration.
7. Software-Generated Interrupts
- Allows software to trigger interrupts.
- Commonly used for RTOS scheduling, debugging, and testing.
8. Fast Interrupt Processing
- Reduces interrupt latency.
- Improves response in motor control, robotics, automotive, and industrial systems.
Types of Interrupt Controllers
Different processors use different interrupt controller architectures depending on application requirements.
1. Programmable Interrupt Controller (PIC)
The Programmable Interrupt Controller (PIC) is one of the earliest interrupt controllers used in microprocessor-based systems.
Characteristics
- Supports multiple interrupt inputs
- Programmable interrupt priorities
- Interrupt masking
- Suitable for legacy systems
PICs were commonly used with Intel x86 processors before more advanced controllers became available.
Typical Applications
- Legacy computers
- Industrial controllers
- Older embedded platforms
2. Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is integrated into ARM Cortex-M processors and is one of the most widely used interrupt controllers in embedded systems.
Unlike external interrupt controllers, the NVIC is built directly into the processor core, resulting in lower interrupt latency and improved performance.
Features
- Hardware interrupt nesting
- Vectored interrupt handling
- Configurable priority levels
- Low interrupt latency
- Software-triggered interrupts
- Automatic context handling
Common Devices
- STM32
- NXP LPC series
- Nordic nRF series
- Texas Instruments Tiva C
- Microchip SAM series
3. Generic Interrupt Controller (GIC)
The Generic Interrupt Controller (GIC) is designed for ARM Cortex-A processors used in high-performance embedded and application systems.
Unlike the NVIC, the GIC supports multiple processor cores and manages interrupt distribution across them.
Features
- Multi-core interrupt routing
- Interrupt virtualization
- Priority management
- Shared peripheral interrupts
- Software-generated interrupts
Typical Applications
- Embedded Linux
- Android devices
- Automotive infotainment
- Networking equipment
- Edge AI platforms
4. Advanced Programmable Interrupt Controller (APIC)
The Advanced Programmable Interrupt Controller (APIC) is commonly used in modern x86 processors. It provides efficient interrupt management for multi-core computing systems.
Features
- Multi-core interrupt support
- Local and I/O APIC architecture
- Inter-processor interrupts
- High scalability
Applications
- Desktop computers
- Servers
- High-performance computing
Comparison of Common Interrupt Controllers
| Feature | PIC | NVIC | GIC | APIC |
| Processor Family | Legacy x86 | ARM Cortex-M | ARM Cortex-A | Modern x86 |
| Integrated with CPU | No | Yes | No | Partial |
| Interrupt Nesting | Limited | Yes | Yes | Yes |
| Multi-Core Support | No | No | Yes | Yes |
| Interrupt Latency | Medium | Very Low | Low | Low |
| Typical Applications | Legacy Systems | Microcontrollers | Application Processors | PCs and Servers |
IRQ vs FIQ
ARM processors classify hardware interrupts into two primary categories: Interrupt Request (IRQ) and Fast Interrupt Request (FIQ).
FIQ is intended for extremely time-sensitive operations, while IRQ is used for general interrupt handling.
| Feature | IRQ | FIQ |
| Full Form | Interrupt Request | Fast Interrupt Request |
| Priority | Lower | Higher |
| Response Time | Normal | Faster |
| Typical Usage | UART, GPIO, ADC | Motor Control, Safety Systems |
| Register Support | Standard Registers | Additional Banked Registers |
| Latency | Higher | Lower |
IRQ
IRQ handles routine peripheral events that do not require the fastest possible response.
Common examples include:
- UART communication
- SPI transfers
- I2C communication
- GPIO interrupts
- Timer events
FIQ
FIQ is reserved for high-priority events where every microsecond matters.
Typical applications include:
- Emergency shutdown
- Motor control
- High-speed data acquisition
- Safety monitoring
- Critical industrial control
Because FIQ uses additional banked registers in classic ARM architectures, the processor spends less time saving and restoring context, resulting in faster execution.
Advantages of an Interrupt Controller
Using an interrupt controller offers several advantages over directly connecting peripherals to the processor.
- Reduces CPU workload
- Eliminates unnecessary polling
- Supports multiple interrupt sources
- Improves real-time responsiveness
- Enables interrupt prioritization
- Supports nested interrupts
- Simplifies interrupt management
- Reduces interrupt latency
- Improves overall system reliability
- Enhances processor utilization
These advantages make interrupt controllers a fundamental component in modern embedded systems.
Limitations of an Interrupt Controller
Although interrupt controllers greatly improve system performance, they also introduce certain design considerations.
- Increased hardware complexity
- Incorrect priority settings can delay critical interrupts
- Excessive interrupt nesting may increase stack usage
- Poor ISR design can reduce overall system performance
- Debugging interrupt-related issues can be challenging
- Large systems require careful interrupt planning
Proper firmware design minimizes these limitations.
Uses and Real-World Applications of an Interrupt Controller
Interrupt controllers are used wherever multiple hardware devices need processor attention.
Common Uses
- Managing timer interrupts
- Handling communication peripherals
- Processing external GPIO events
- Coordinating DMA transfers
- Supporting real-time operating systems
- Managing sensor events
- Handling touch-screen inputs
- Processing network packets
- Monitoring safety signals
- Controlling industrial equipment
Industry Applications
- Automotive Electronics
- Industrial Automation
- Medical Devices
- Consumer Electronics
- Internet of Things (IoT)
- Robotics
- Aerospace and Defense
ARM Generic Interrupt Controller (GIC) Architecture
The Generic Interrupt Controller (GIC) is designed for ARM Cortex-A processors that power embedded Linux systems and other high-performance platforms.
Unlike the NVIC, which is optimized for single-core microcontrollers, the GIC manages interrupts across one or more processor cores and supports interrupt distribution between them.
Its architecture includes:
- Distributor
- CPU Interface
- Redistributor (in newer GIC versions)
- Interrupt Priority Registers
- Interrupt Configuration Registers
The GIC is widely used in:
- Embedded Linux devices
- Android platforms
- Automotive infotainment systems
- Industrial gateways
- AI edge computing systems
Its scalability and multi-core support make it suitable for complex embedded applications where several processors must share interrupt sources.
Interrupt Handling Workflow
The following workflow illustrates how an interrupt controller manages an interrupt from the moment a hardware event occurs until the processor resumes normal execution.
Hardware Event
│
▼
Peripheral Generates Interrupt
│
▼
Interrupt Controller Receives Request
│
▼
Interrupt Enabled?
│
┌────┴────┐
│ │
No Yes
│ │
Discard ▼
Check Priority
│
▼
Select Highest-Priority Interrupt
│
▼
CPU Saves Current Context
│
▼
Execute Interrupt Service Routine (ISR)
│
▼
Clear Interrupt Flag
│
▼
Restore CPU Context
│
▼
Resume Main Program
Interrupt Polling vs Interrupt Controller
| Feature | Polling | Interrupt Controller |
| CPU Usage | High | Low |
| Response Time | Depends on polling interval | Immediate |
| Power Consumption | Higher | Lower |
| Efficiency | Lower | Higher |
| Suitable for Real-Time Systems | Limited | Yes |
| Scalability | Poor | Excellent |
| Processor Overhead | High | Low |
Polling is simple to implement but becomes inefficient as the number of peripherals increases. Interrupt-driven systems allow the processor to perform useful work until an event actually requires attention.
Conclusion
An Interrupt Controller is a critical component that enables processors to respond efficiently to hardware events from multiple peripherals. By prioritizing interrupt requests, supporting masking and nesting, and directing the CPU to the correct Interrupt Service Routine, it improves responsiveness and reduces processor overhead.
Whether working with ARM Cortex-M microcontrollers using the NVIC or Cortex-A processors using the GIC, understanding interrupt controllers is essential for developing reliable and efficient embedded systems. Mastering this concept also provides a strong foundation for learning interrupt programming, RTOS scheduling, Linux device drivers, and advanced firmware development.
