Efficient handling of interrupts is critical in embedded systems and processors, ensuring seamless communication between hardware components. Interrupt controllers play a vital role in managing interrupt requests, prioritizing them, and directing them to the appropriate handlers without overloading the CPU.
There are several types of interrupt controllers, each designed for specific applications and architectures. These include:
🔹 Generic Interrupt Controller (GIC) – Ideal for multicore processors, enabling shared and private interrupts.
🔹 Nested Vector Interrupt Controller (NVIC) – Optimized for Cortex-M microcontrollers, reducing interrupt latency.
🔹 Vector Interrupt Controller (VIC) – Allows direct execution of ISRs, enhancing response times.
🔹 Wake-up Interrupt Controller (WIC) – Facilitates power-efficient wake-ups from low-power states.
Interrupt controllers come in numerous varieties, reflecting the diverse configurations found in their hardware design. Here are the most frequently encountered types of interrupt controllers.
Generic Interrupt Controller (GIC)
Nested Vector Interrupt Controller (NVIC)
Vector Interrupt Controller (VIC)
Wake-up Interrupt Controller (WIC)
This type of interrupt controller is commonly employed in multicore environments where communication between processors is essential. The GIC operates as a type of non-vectored interrupt controller. An interrupt ID differentiates between various interrupts. There are four distinct states for an interrupt request: Active, Pending, Inactive, and a state that combines both Active and Pending. The GIC offers a range of supported features, as outlined below
Multiple cores can be configured to share a single interrupt originating from one or more peripheral sources.
Private Peripheral Interrupt (PPI): An interrupt can be aimed at a particular core, contingent upon the configuration of the core. The target interrupt is kept confidential for the designated core.
Certain interrupts initiated by the software will facilitate communication between processors. The GIC features both IRQ and FIQ lines interfacing with the processor.
The NVIC processor allows for handling the interrupt service routine (ISR) without the necessity of polling the interrupt status register to ascertain the source of an interrupt. In the memory (Vector table area), there is a predefined mapping for the ISR that requires the targeted ISR Callback to be added in the order corresponding to the interrupt number.
The NVIC is characterized by its lightweight nature, which includes a limited number of supported interrupts aimed at lowering interrupt latency, and it demands only a few kilobytes of RAM and Flash memory. Functioning at a frequency under 100 MHz, it is perfectly tailored for the Cortex-M series of microcontroller units
Enables the execution of the ISR callback once the interrupt has been triggered. The VIC is equipped with 32 interrupt request inputs that can be programmed to fall into one of three categories: FIQ, vectored IRQ, or non-vectored IRQ. Listed below are various features that are supported by the VIC.
The WIC is an optional hardware component found in the NVIC, designed to wake the processor in just a few clock cycles while restoring its last operational state.
WIC serves as the mechanism for the processor to enter and exit low-power and ultra-low-power states. The power management controller of the processor is directly connected to WIC via hardware signals for effective control. WIC does not function as a programmable entity. The only supported configuration is the ability to enable or disable WIC on an interrupt line.
Indian Institute of Embedded Systems – IIES